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IR3086
PRELIMINARY DATA SHEET XPHASETM PHASE IC WITH OVP, FAULT AND OVERTEMP DETECT
DESCRIPTION
The IR3086 Phase IC combined with an IR XPhaseTM Control IC provides a full featured and flexible way to implement power solutions for the latest high performance CPUs and ASICs. The "Control" IC provides overall system control and interfaces with any number of "Phase" ICs which each drive and monitor a single phase of a multiphase converter. The XPhaseTM architecture results in a power supply that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches.
FEATURES
* * * * * * * * * * * * *
2.5A Average Gate Drive Current Loss-Less Inductor Current Sense Internal Inductor DCR Temperature Compensation Programmable Phase Delay Programmable Feed-Forward Voltage Mode PWM Ramp Sub 100ns Minimum Pulse Width supports 1MHz per-phase operation Current Sense Amplifier drives a single wire Average Current Share Bus Current Share Amplifier reduces PWM Ramp slope to ensure sharing between phases Body BrakingTM disables Synchronous MOSFET for improved transient response and prevents negative ee DataSh output voltage at converter turn-off OVP comparator with 150ns response .com Phase Fault Detection Programmable Phase Over-Temperature Detection Small thermally enhanced 20L MLPQ package
PACKAGE PINOUT
19
20
18
17 CSIN-
1 2 3 4 5
PHSFLT
BIASIN
DACIN
CSIN+
16
RMPIN+ RMPINHOTSET VRHOT ISHARE SCOMP EAIN
VCCH
15 14 13 12 11
IR3086 PHASE IC
PWMRMP LGND VCC 10
GATEH PGND GATEL VCCL
6
7
8
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IR3086
ORDERING INFORMATION
Device IR3086MTR IR3086M
Order Quantity 3000 5 per Bag
ABSOLUTE MAXIMUM RATINGS
Operating Junction Temperature.................150oC Storage Temperature Range......................-65oC to 150oC ESD Rating.............................................HBM Class 1C JEDEC standard
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PIN NAME RMPIN+ RMPINHOTSET VRHOT ISHARE SCOMP EAIN PWMRMP LGND VCC VCCL GATEL PGND GATEH VCCH CSIN+ CSINPHSFLT DACIN BIASIN
VMAX
VMIN
ISOURCE 1mA 1mA 1mA 1mA 5mA 1mA 1mA 1mA 50mA n/a n/a 3A for 100ns, 200mA DC 3A for 100ns, 200mA DC 3A for 100ns, 200mA DC n/a 1mA 1mA 1mA 1mA 1mA
ISINK 1mA 1mA 1mA 30mA 5mA 1mA 1mA 20mA n/a 50mA 3A for 100ns, 200mA DC 3A for 100ns, 200mA DC n/a 3A for 100ns, 200mA DC 3A for 100ns, 200mA DC 1mA 1mA 20mA 1mA 1mA
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20V -0.3V 20V -0.3V 20V -0.3V 20V -0.3V 20V -0.3V 20V -0.3V .com 20V -0.3V 20V -0.3V n/a n/a 24V -0.3V 27V -0.3V 27V 0.3V 27V 27V 20V 20V 20V 20V 20V -0.3V DC, -2V for 100ns -0.3V -0.3V DC, -2V for 100ns -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V
ee DataSh
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IR3086
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over: 8.4V VCC 14V, 6V VCCH 25V, 6V VCCL 14V, and 0 oC TJ 125 oC, CGATEH = 3.3nF, CGATEL = 6.8nF PARAMETER Gate Drivers GATEH Rise Time GATEH Fall Time GATEL Rise Time GATEL Fall Time GATEL low to GATEH high delay GATEH low to GATEL high delay
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TEST CONDITION VCCH = 12V, Measure 2V to 9V transition time VCCH = 12V, Measure 9V to 2V transition time VCCL = 12V, Measure 2V to 9V transition time VCCL = 12V, Measure 9V to 2V transition time VCCH = VCCL = 12V, Measure the time from GATEL falling to 1V to GATEH rising to 1V VCCH = VCCL = 12V, Measure the time from GATEH falling to 1V to GATEL rising to 1V Force GATH or GATEL = 2V with BIASIN = 0V
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MIN
TYP 22 22 50 50
MAX 50 50 75 75 50
UNIT ns ns ns ns ns
10
25
10
25
50
ns
Disable Pull-Down Current Current Sense Amplifier CSIN+ Bias Current CSIN- Bias Current Input Offset Voltage Gain at TJ = 25 oC Gain at TJ = 125 oC Slew Rate
15
25
40
A
ee DataSh
CSIN+ = CSIN- = DACIN. Measure input referred offset from DACIN
-0.5 -1 -3 32 27
-0.25 -0.4 0.5 34 29 12.5
0 0 5 36 31
A A mV V/V V/V V/s
Current Sense Amp output is an internal node. Slew rate at the ISHARE pin will be set by the internal 10k resistor and any stray external capacitance -20 0 7.9 9.3 Force I(PWMRMP) = 500A. Measure V(PWMRMP) - V(DACIN) -10 4 20 -10 -1 100
Differential Input Range Common Mode Input Range Rout at TJ = 25 oC Rout at TJ = 125 oC Ramp Discharge Clamp Clamp Voltage Clamp Discharge Current Ramp Comparator Input Offset Voltage Hysteresis RMPIN+, RMPIN- Bias Current Propagation Delay
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10.5 12.4 5 8 40 0 -0.5 150
100 4 13.1 15.5 20
mV V k k mV mA
Note 1
80 10 1 240
mV mV A ns
VCCH = 12V. Measure time from RMPIN input (50mV overdrive) to GATEL transition to <11V.
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PARAMETER PWM Comparator PWM Comparator Input Offset Voltage EAIN & PWMRMP Bias Current Propagation Delay TEST CONDITION MIN -5 Clamp and Current Share Adjust OFF VCCH = 12V. Measure time from PWMRMP input (50mV overdrive) to GATEH transition to < 11V. Exceeding the Common Mode input range results in 100% duty cycle 10 -3.5 4 0.9 20 60 -1 TYP 5 -0.4 70 MAX 15 1 150 UNIT mV A ns
Common Mode Input Range Share Adjust Error Amplifier Input Offset Voltage Input Voltage Range PWMRMP Adjust Current Transconductance SCOMP Source/Sink Current SCOMP Activation Voltage
5
V
20 8 1.6 30 150
EAIN - PWMRMP, Note 1 I(PWMRMP) = 3.5mA, Note 1 Note 1 Amount SCOMP must increase from its minimum voltage until the Ramp Slope Adjust current equals = 10A I(PWMRMP) = 500A
.com Compare to V(DACIN) VCCL = 12V. Measure time from EAIN < 0.9 x V(DACIN) (200mV overdrive) to GATEL transition to < 11V. Note 1.
30 3.5 2.3 40 300
mV V mA A/V A mV
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PWMRMP Min Voltage 0% Duty Cycle Comparator Threshold Voltage Propagation Delay
150 88
225 91 100
350 94 150
mV % ns
ee DataSh
OVP Comparator Threshold Voltage Propagation Delay
Compare to V(DACIN) VCCL = 12V. Measure time from CSIN > V(DACIN) (200mV overdrive) to GATEL transition to <11V. Compare to V(DACIN) I(PHSFLT) = 4mA V(PHSFLT) = 5.5V
100
125 150
160 250
mV ns
Phase Fault Comparator Threshold Voltage Output Voltage PHSFLT Leakage Current VRHOT Comparator HOTSET Bias Current Output Voltage VRHOT Leakage Current Threshold Hysteresis Threshold Voltage
88
91 300 0 -0.5 150 0 7.0
94 400 10
% mV A A mV A o C V
-2 I(VRHOT) = 29mA V(VRHOT) = 5.5V TJ 85 oC TJ 85 oC MIN 4.73mV/ oC x TJ + 1.176V
3.0 TYP 4.73mV/ oC x TJ + 1.241V
1 400 10 9.0 MAX 4.73mV/ oC x TJ + 1.356V
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IR3086
PARAMETER General VCC Supply Current VCCL Supply Current VCCH Supply Current BIASIN Bias Current DACIN Bias Current Note 1: Guaranteed by design, but not tested in production TEST CONDITION MIN TYP 10 2.5 5.5 6.5 -2.5 -0.5 MAX 14 5 8 10 2 1 UNIT mA mA mA mA A A
6V VCCH 14V 14V VCCH 25V -5 -2
PIN DESCRIPTION
PIN# 1 2 3
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PIN SYMBOL RMPIN+ RMPINHOTSET
4 5
VRHOT ISHARE
6 7 8 9 10 11 12 13 14 15 16 17 18
SCOMP EAIN PWMRMP LGND VCC VCCL GATEL PGND GATEH VCCH CSIN+ CSINPHSFLT
19
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DACIN BIASIN
PIN DESCRIPTION Non-inverting input to Ramp Comparator Inverting input to Ramp Comparator Inverting input to VRHOT comparator. Connect resistor divider from VBIAS to LGND to program VRHOT threshold. Diode or thermistor may be substituted for lower resistor for enhanced/remote temperature sensing. Open Collector output of the VRHOT comparator which drives low if IC junction ee DataSh temperature exceeds the user programmable limit. Connect external pull-up. .com Output of the Current Sense Amplifier and input to the Share Adjust Error Amplifier. Voltage on this pin is equal to V(DACIN) + 34 [V(CSIN+) - V(CSIN-)]. Connecting ISHARE pins creates a Share Bus enabling current sharing between Phase ICs. The Share bus is also used by the Control IC for voltage positioning and OverCurrent protection. Compensation for the Current Share control loop. Connect a capacitor to ground to set the control loop's bandwidth. PWM comparator input from the Control IC. Both Gate Driver outputs drive low if the voltage on this pin is less than 91% of V(DACIN). PWM comparator ramp input. Connect a resistor from this pin to the converter input voltage and a capacitor to LGND to program the PWM ramp. Signal ground and IC substrate connection Power for internal circuitry Power for Low-Side Gate Driver Low-Side Gate Driver Output and input to GATEH non-overlap comparator Return for Gate Drivers High-Side Gate Driver Output and input to GATEL non-overlap comparator Power for High-Side Gate Driver Non-inverting input to the Current Sense Amplifier Inverting input to the Current Sense Amplifier and non-inverting input to the OVP comparator Open Collector output of the Phase Fault comparator. Drives low if Phase current is unable to match the level of the SHARE bus due to an external fault. Connect external pull-up. Reference voltage input from the Control IC and inverting input to the OVP comparator. Current sensing and PWM operation referenced to this pin. System reference voltage for internal circuitry 9/1/03
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IR3086
SYSTEM THEORY OF OPERATION
XPhaseTM Architecture The XPhaseTM architecture is designed for multiphase interleaved buck converters which are used in applications requiring small size, design flexibility, low voltage, high current and fast transient response. The architecture can be used in any multiphase converter ranging from 1 to 16 or more phases where flexibility facilitates the design trade-off of multiphase converters. The scalable architecture can be applied to other applications which require high current or multiple output voltages. As shown in Figure 1, the XPhaseTM architecture consists of a Control IC and a scalable array of phase converters each using a single Phase IC. The Control IC communicates with the Phase ICs through a 5-wire analog bus, i.e. bias voltage, phase timing, average current, error amplifier output, and VID voltage. The Control IC incorporates all the system functions, i.e. VID, PWM ramp oscillator, error amplifier, bias voltage, and fault protections etc. The Phase IC implements the functions required by the converter of each phase, i.e. the gate drivers, PWM comparator and latch, over-voltage protection, and current sensing and sharing.
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There is no unused or redundant silicon with the XPhaseTM architecture compared to others such as a 4 phase controller that can be configured for 2, 3, or 4 phase operation. PCB Layout is easier since the 5 wire bus eliminates the need for point-to-point wiring between the Control IC and each Phase. The critical gate drive and current sense connections are short and local to the Phase ICs. This improves the PCB layout by lowering the parasitic inductance of the gate drive circuits and reducing the noise of the current sense signal. ee DataSh
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POWER GOOD PHASE FAULT VR HOT
12V
ENABLE
VID5 VID0 VID1 VID2 VID3 VID4
IR3081 CONTROL IC
PHASE FAULT >> BIAS VOLTAGE >> PHASE TIMING << CURRENT SENSE >> PWM CONTROL >> VID VOLTAGE PHASE HOT CCS RCS CURRENT SHARE CIN VOUT SENSE+
IR3086 PHASE IC
VOUT+ 0.1uF COUT VOUT-
VOUT SENSE-
PHASE FAULT
CURRENT SHARE
IR3086 PHASE IC
0.1uF
PHASE HOT CCS RCS
CONTROL BUS
ADDITIONAL PHASES
INPUT/OUTPUT
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Figure 1 - System Block Diagram Page 6 of 15
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PWM Control Method The PWM block diagram of the XPhaseTM architecture is shown in Figure 2. Feed-forward voltage mode control with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used for the voltage control loop. An external RC circuit connected to the input voltage and ground is used to program the slope of the PWM ramp and to provide the feed-forward control at each phase. The PWM ramp slope will change with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change due to variations in the silver box output voltage or due to drops in the PCB related to changes in load current.
VIN
CONTROL IC
BIASIN
50% DUTY CYCLE
PHASE IC
SYSTEM REFERENCE VOLTAGE CLOCK PULSE GENERATOR
+
RAMP GENERATOR
VPEAK
RMPOUT
RAMPIN+
-
PWM LATCH S PWM COMPARATOR
+ RESET DOMINANT
GATEH
VOSNS+ VOUT
COUT
VVALLEY
RRAMP1
RAMPINEAIN
VBIAS
R
GATEL
+ VBIAS REGULATOR
VDAC VOSNS-
RRAMP2
GND
PWMRMP
RPWMRMP
VDAC
EAOUT
CPWMRMP
SCOMP SHARE ADJUST ERROR AMP ISHARE 10K
RAMP DISCHARGE CLAMP
+
-
CSCOMP
ERROR AMP
RVFB
+
20mV
IFB
IROSC VDRP AMP
RDRP
X34 DACIN
VDRP
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PHASE IC
BIASIN RAMPIN+
+ -
IIN
SYSTEM REFERENCE VOLTAGE CLOCK PULSE GENERATOR S PWM COMPARATOR
+
PWM LATCH
RRAMP1
RAMPINEAIN
RESET DOMINANT
R
RRAMP2
PWMRMP
RPWMRMP
CPWMRMP
SCOMP SHARE ADJUST ERROR AMP ISHARE 10K
RAMP DISCHARGE CLAMP
CSCOMP
+
20mV
X34 DACIN
Figure 2 - PWM Block Diagram Frequency and Phase Timing Control An oscillator with programmable frequency is located in the Control IC. The output of the oscillator is a 50% duty cycle triangle waveform with peak and valley voltages of approximately 5V and 1V. This signal is used to program both the switching frequency and phase timing of the Phase ICs. The Phase IC is programmed by resistor divider RRAMP1 and RRAMP2 connected between the VBIAS reference voltage and the Phase IC LGND pin. A comparator in the Phase ICs detects the crossing of the oscillator waveform with the voltage generated by the resistor divider and triggers a clock pulse that starts the PWM cycle. The peak and valley voltages track the VBIAS voltage reducing potential Phase IC timing errors. Figure 3 shows the Phase timing for an 8 phase converter. Note that both slopes of the triangle waveform can be used for synchronization by swapping the RAMP + and - pins. .com Page 7 of 15
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+
-
-
+
-
RAMP SLOPE ADJUST
ENABLE
O% DUTY CYCLE COMPARATOR
+ -
X 0.91
CURRENT SENSE AMP
+
-
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FB
-
+ + + -
RAMP SLOPE ADJUST
ENABLE
O% DUTY CYCLE COMPARATOR
+ -
VOSNS-
+
-
+ -
X 0.91
CURRENT SENSE AMP
CSIN+
CCS RCS
CSIN-
ee DataSh
GATEH
GATEL
CSIN+
CCS RCS
CSIN-
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IR3086
50% RAMP DUTY CYCLE SLOPE = 80mV / % DC
RAMP (FROM CONTROL IC)
VPEAK (5.0V) VPHASE4&5 (4.5V) VPHASE3&6 (3.5V) VPHASE2&7 (2.5V) VPHASE1&8 (1.5V) VVALLEY (1.00V)
SLOPE = 1.6mV / ns @ 200kHz SLOPE = 8.0mV / ns @ 1MHz
CLK1
CLK2
PHASE IC CLOCK PULSES
CLK3
CLK4
CLK5
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CLK6
ee DataSh
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CLK7
CLK8
Figure 3 - 8 Phase Oscillator Waveforms PWM Operation The PWM comparator is located in the Phase IC. Upon receiving a clock pulse, the PWM latch is set, the PWMRMP voltage begins to increase, the low side driver is turned off, and the high side driver is then turned on. When the PWMRMP voltage exceeds the Error Amp's output voltage the PWM latch is reset. This turns off the high side driver, turns on the low side driver, and activates the Ramp Discharge Clamp. The clamp quickly discharges the PWMRMP capacitor to the VDAC voltage of the Control IC until the next clock pulse. The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. An Error Amp output voltage greater than the common mode input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement guarantees the Error Amp is always in control and can demand 0 to 100% duty cycle as required. It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of most systems. The inductor current will increase much more rapidly than decrease in response to load transients. This control method is designed to provide "single cycle transient response" where the inductor current changes in response to load transients within a single switching cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. An additional advantage is that differences in ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC. .com Page 8 of 15
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IR3086
Body BrakingTM In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; TSLEW = [L x (IMAX - IMIN)] / Vout The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the synchronous rectifier's body diode occurs. This increases the voltage across the inductor from Vout to Vout + VBODY DIODE. The minimum time required to reduce the current in the inductor in response to a load transient decrease is now; TSLEW = [L x (IMAX - IMIN)] / (Vout + VBODY DIODE) Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be increased by 2X or more. This patent pending technique is referred to as "body braking" and is accomplished through the "0% Duty Cycle Comparator" located in the Phase IC. If the Error Amp's output voltage drops below 91% of the VDAC voltage this comparator turns off the low side gate driver. Figure 4 depicts PWM operating waveforms under various conditions
PHASE IC CLOCK PULSE
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EAIN PWMRMP VDAC
ee DataSh
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91% VDAC
GATEH
GATEL
STEADY-STATE OPERATION
DUTY CYCLE INCREASE DUE TO LOAD INCREASE
DUTY CYCLE DECREASE DUE TO VIN INCREASE (FEED-FORWARD)
DUTY CYCLE DECREASE DUE TO LOAD DECREASE (BODY BRAKING) OR FAULT (VCC UV, VCCVID UV, OCP, VID=11111X)
STEADY-STATE OPERATION
Figure 4 - PWM Operating Waveforms Lossless Average Inductor Current Sensing Inductor current can be sensed by connecting a resistor and a capacitor in parallel with the inductor and measuring the voltage across the capacitor. The equation of the sensing network is,
vC ( s ) = v L ( s )
R + sL 1 = iL (s) L 1 + sRS C S 1 + sRS C S
Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time constant of the inductor which is the inductance L over the inductor DCR. If the two time constants match, the voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of inductor DC current, but affects the AC component of the inductor current.
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IR3086
The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in series with inductor, this is the only sense method that can support a single cycle transient response. Other methods provide no information during either load increase (low side sensing) or load decrease (high side sensing). An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional sources of peak-to-average errors. Current Sense Amplifier A high speed differential current sense amplifier is located in the Phase IC, as shown in figure 5. Its gain decreases with increasing temperature and is nominally 34 at 25C and 29 at 125C (-1470 ppm/C). This reduction of gain tends to compensate the 3850 ppm/C increase in inductor DCR. Since in most designs the Phase IC junction is hotter than the inductor these two effects tend to cancel such that no additional temperature compensation of the load line is required.
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The current sense amplifier can accept positive differential input up to 100mV and negative up to -20mV before clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the Control IC and other Phases through an on-chip 10K resistor connected to the ISHARE pin. The ISHARE pins of all the phases are ataShee D tied together and the voltage on the share bus represents the total current being delivered to the load and is used by .com the Control IC for voltage positioning and current limit protection.
vL iL L Rs CSA CO RL Cs vc Vo Co
Figure 5 - Inductor Current Sensing and Current Sense Amplifier Average Current Share Loop Current sharing between phases of the converter is achieved by the average current share loop in each Phase IC. The output of the current sense amplifier is compared with the share bus less a 20mV offset. If current in a phase is smaller than the average current, the share adjust error amplifier of the phase will activate a current source that reduces the slope of its PWM ramp thereby increasing its duty cycle and output current. The crossover frequency of the current share loop can be programmed with a capacitor at the SCOMP pin so that the share loop does not interact with the output voltage loop.
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IR3086
IR3086 THEORY OF OPERATION
Block Diagram The Block diagram of the IR3086 is shown in figure 6 and specific features discussed in the following section.
RAMP COMPARATOR
-
PWM LATCH CLOCK PULSE GENERATOR S PWM COMPARATOR
+ RESET DOMINANT
VCCH GATEH
RMPINEAIN BIASIN PWMRMP
+
ENABLE +
RAMP SLOPE ADJUST SCOMP SHARE ADJUST ERROR AMP ISHARE 10K LGND VRHOT COMPARATOR
+
X 0.91
-
0% DUTY CYCLE COMPARATOR
-
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OVP COMPARATOR
+
130mV
+
20mV
+
-
CURRENT + SENSE AMP .com + X34
HOTSET
-
Figure 6 - IR3086 Block Diagram
Tri-State Gate Drivers The gate drivers can deliver up to 3A peak current. An adaptive non-overlap circuit monitors the voltage on the GATEH and GATEL pins to prevent MOSFET shoot-through current while minimizing body diode conduction. An Enable signal is provided by the Control IC to the Phase IC without the additional of a dedicated signal line. The Error Amplifier output of the Control IC drives low in response to any fault condition such as input under voltage or output overload. The IR3086 0% duty cycle comparator detects this and drives both gate outputs low. This tri-state operation prevents negative inductor current and negative output voltage during power-down. The Gate Drivers revert to a high impedance "off" state at VCCL and VCCH supply voltages below the normal operating range. An 80k resistor is connected across the GATEX and PGND pins to prevent the GATEX voltage from rising due to leakage or other cause under these conditions.
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-
+
VOLTAGE PROPORTIONAL TO ABSOLUTE TEMPERATURE
+
VRHOT
-
RAMP DISCHARGE CLAMP
+
-
+
-
-
-
-
+
RMPIN+
R
-
SYSTEM REFERENCE VOLTAGE
GATE NON-OVERLAP COMPARATORS
+
2V
VCCL GATEL PGND
+ -
INTERNAL CIRCUIT BIAS
VCC
+
DACIN CSIN+ CSINPHSFLT FAULT COMPARATOR
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IR3086
Over Voltage Protection (OVP) The IR3086 includes over-voltage protection that turns on the low side MOSFET to protect the load in the event of a shorted high-side MOSFET or connection of the converter output to an excessive output voltage. A comparator monitors the voltage at the CSIN- pin which is usually connected directly to the converter output. If the voltage exceeds the DACIN voltage plus 130mV the GATEL pin drives high. The OVP circuit over-rides the normal PWM operation and will fully turn-on the low side MOSFET within approximately 150ns. The low side MOSFET will remain ON until the over-voltage condition ceases. When designing for OVP the overall system must be considered. In many cases the over-current protection of the ACDC or DC-DC converter supplying the multiphase converter will be triggered thus providing effective protection without damage as long as all PCB traces and components are sized to handle the worst-case maximum current. If this is not possible a fuse can be added in the input supply to the multiphase converter. One scenario to be careful of is where the input voltage to the multiphase converter may be pulled below the level where the ICs can provide adequate voltage to the low side MOSFET thus defeating OVP. Dynamic changes in the VID code to a lower output voltage may trigger OVP. For example; a 250mV decrease in output voltage combined with a light load condition will cause the low side MOSFETs to turn on and interfere with Body BrakingTM. This will not cause a problem however as Body BrakingTM will resume once the output voltage is less than 130mV above the VID voltage.
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ee DataSh Excessive distribution impedance between the.com or programming of the converter output voltage converter and load above the VID voltage may trigger OVP during normal operation. If the voltage dropped across the distribution impedance exceeds the minimum OVP comparator threshold of 100mV plus any voltage positioning the IR3086 can not be used. For example; a converter having 25mV of VID offset, 125mV of AVP at full load, and 75mV of drop in the distribution path at full load would be OK since 100mV + 25mV + 125mV = 250mV which is greater than 75mV. The IR3088 Phase IC without OVP should be used in applications with excessive distribution impedance.
Thermal Monitoring (VRHOT) The IR3086 senses its own die temperature and produces a voltage at the input of the VRHOT comparator that is proportional to temperature. An external resistor divider connected from VBIAS to the HOTSET pin and ground can be used to program the thermal trip point of the VRHOT comparator. The VRHOT pin is an open-collector output and should be pulled up to a voltage source through a resistor. If the thermal trip point is reached the VRHOT output drives low. Phase Fault Its possible for multiphase converters to appear to be working correctly with one or more phases not functioning. The output voltage can still be regulated and the full load current may still be delivered. However, the remaining phase(s) will be stressed far beyond their intended design limits and are likely to fail. Loss of a phase can occur due to poor solder connections or mounting during the manufacturing process, or can occur in the field. The most common failure mode of a buck converter is failure of the high side MOSFET.
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IR3086
The IR3086 has the ability to detect if a phase stops switching and can provide this information to the system through the PHSFLT output pin. If a phase stops switching its output current will drop to zero and the output of its IR3086 current sense amp will be the DACIN voltage. The Share Adjust Amplifier reacts to this by increasing the Ramp Slope Adjust current until it exceeds the externally programmable PWM Ramp bias current. This will cause the voltage at the PWMRMP pin to drop below its normal operating range. The Fault Comparator trips and drives the PHSFLT output to ground when the voltage on the PWMRMP pin falls below 91% of the DACIN voltage. PHSFLT is an open-collector output and should be pulled up to a voltage source through a resistor.
APPLICATIONS INFORMATION
POWERGOOD VRHOT PHASE FAULT
12V
RCS-
10 CCSRBIASIN 20 19 18 RPHASE1 17 16
CCS+
CIN
RCS+ 0.1uF
PHSFLT
BIASIN
DACIN
CSIN+
CSIN-
0.1uF
1 2 RSS/DEL 3 4 0.1uF 5 RPHASE2
RMPIN+ RMPINHOTSET VRHOT ISHARE SCOMP EAIN
VCCH
15 14 13 12 11 DISTRIBUTION IMPEDANCE COUT
VOUT SENSE+
IR3086 PHASE IC
PWMRMP LGND VCC
GATEH PGND GATEL VCCL
VOUT+
ENABLE
28 26 27
CSS/DEL
VOUT0.1uF 10 RPWMRMP
24
23
25
22
6
7
CPWMRMP 8
9
10
RVFB
RVFB
VOUT SENSE-
ENABLE
PWRGD
SS/DEL
N/C
LGND
RMPOUT
VCC
1
OSCDS VID5 VID0 VID1 VID2 VID3
VBIAS BBFB
21 20 19 18 17 16 15 RVDRP
RPHASE3
VID5 VID0 VID1
CSCOMP
2 3 4 5 6 7
0.1uF
VOSNS-
ROSC
TRM1
TRM2
TRM3
TRM4
VDAC
20
19
18
17
RPHASE1
16
t4U.com
VID2 VID3 VID4
IR3081 CONTROL IC
EAOUT FB VDRP IIN OCSET
RCS-
CCSRBIASIN RVDRP
CCS+
VID4
RCS+ 0.1uF
ROCSET
1 2 3 4 5 CVDAC RPHASE2
PHSFLT
BIASIN
DACIN
CSIN+
CSIN-
10
11
12
13
14
ee DataSh
8
9
RMPIN+ RMPIN-
VCCH
15 14 13 12 11
ROSC
RVDAC
RSHARE
.com
HOTSET VRHOT ISHARE SCOMP 6 RPHASE3
IR3086 PHASE IC
PWMRMP LGND EAIN VCC
GATEH PGND GATEL VCCL
0.1uF 10 RPWMRMP
7
CPWMRMP 8
9
CSCOMP
10
0.1uF
RCS-
CCSRBIASIN 19 20 18 17 RPHASE1 16
CCS+
RCS+ 0.1uF
BIASIN
DACIN
1 2 3 4 5 RPHASE2
PHSFLT
CSIN+
CSIN-
RMPIN+ RMPINHOTSET VRHOT ISHARE SCOMP EAIN
VCCH
15 14 13 12 11
IR3086 PHASE IC
PWMRMP LGND VCC
GATEH PGND GATEL VCCL
0.1uF 10 RPWMRMP
6
7
CPWMRMP 8
9
RPHASE3
CSCOMP
10
0.1uF
RCS-
CCS+ RBIASIN 20 19 18 RPHASE1 17 16 CCSRCS+ 0.1uF
BIASIN
DACIN
1 2 3 4 5 RPHASE2
PHSFLT
CSIN+
CSIN-
RMPIN+ RMPINHOTSET VRHOT ISHARE SCOMP EAIN
VCCH
15 14 13 12 11
IR3086 PHASE IC
PWMRMP LGND VCC
GATEH PGND GATEL VCCL
0.1uF 10 RPWMRMP
6
7
CPWMRMP 8
9
RPHASE3
CSCOMP
10
0.1uF
RCS-
CCS+ RBIASIN 19 20 18 RPHASE1 17 16 CCSRCS+ 0.1uF
BIASIN
DACIN
1 2 3 4 5 RPHASE2
PHSFLT
CSIN+
CSIN-
RMPIN+ RMPINHOTSET VRHOT ISHARE SCOMP EAIN
VCCH
15 14 13 12 11
IR3086 PHASE IC
PWMRMP LGND VCC
GATEH PGND GATEL VCCL
0.1uF 10 RPWMRMP
6
7
CPWMRMP 8
9
RPHASE3
CSCOMP
10
0.1uF
Figure 7 - 5 Phase IR3081/3086 EVRD10 Converter
.com
Page 13 of 15
.com DataSheet 4 U .com
9/1/03
www..com
IR3086
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. * * * * * Dedicate at least one middle layer for a ground plane, which is then split into signal ground plane (LGND) and power ground plane (PGND). Connect PGND to LGND pins of each phase IC to the ground tab under it. In order to reduce the noise coupled to SCOMP pin of phase ICs, use a dedicated wire to connect the capacitor CSCOMP to LGND pin, but connect PWM ramp capacitor CPWMRMP, phase delay programming resistor RRAMP2, decoupling capacitor CVCC to LGND plane through vias. Connect the decoupling capacitor low side gate driver CVCCL and the ground tab under the phase IC to PGND plane through vias. Place the decoupling capacitor CVCC as close as possible to VCC pin of the control IC, and place the decoupling capacitors CVCC and CVCCL as close as possible to VCC and VCCL pins of the phase IC respectively. Bus signals should not cross over the fast transition nodes, such as switching nodes and gate drive output.
* *
t4U.com
* *
Use Kelvin connections for the current sense signals, and use the ground plane to shield the current sense traces. ee DataSh Place the phase ICs as close as possible to the MOSFETs to reduce the parasitic resistance and .com inductance of the gate drive paths. Place the input capacitors close to the drain of top MOSFET and the source of bottom MOSFET. Replace the bigger-package ceramic capacitors with multiple smaller-package ones to reduce the parasitic inductance. There are two switching power loops. One loop includes the input capacitors, top MOSFET, inductor, output capacitors and the load; another loop consists of bottom MOSFET, inductor, output capacitors and the load. Route the switching power paths using wide and short traces or polygons; use multiple vias for connections between layers.
LGND PLANE
To VIN To LGND Plane CPWMRMP To Signal Bus To LGND Plane To Gate Drive Voltage RRAMP1
*
RPWMRMP
EAIN
RRAMP2
HOTSET
ISHARE
RMPIN-
VRHOT
RMPIN+
SCOMP EAIN
BIASIN DACIN PHSFLT or OPTIPHS CSINCSIN+
CSCOMP
RBIASIN
PWMRMP LGND
GATEL
GATEH
PGND
VCCL
VCCH
To LGND Plane
CVCC
VCC
CCS1 RCS1
CVCCL To PGND Plane
CVCCH
RCS2
To MOSFETs To To Inductor Switching Current Sensing Node
.com
PGND PLANE
Figure 8 - Layout of Phase IC Components Page 14 of 15
.com DataSheet 4 U .com
DVCCH CCS2
9/1/03
www..com
IR3086
PACKAGE INFORMATION
20L MLPQ (4 x 4 mm Body) - JA = 32oC/W, JC = 3oC/W
4.40 - 5.00 4.00 2.90 1.20 Holes: 0.3-0.33 2.15
t4U.com
0.23 2.15 2.90 4.00 4.40 - 5.00
.com 0.50
0.75-1.05
Note: All dimensions are in Millimeters.
Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. .com www.irf.com Page 15 of 15
.com DataSheet 4 U .com
9/1/03

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